:: About Us ::

Performance Direct
GeIL's production philosophy puts integration above component distribution. Top-down single company, no-fault operation: from DRAM design commencement, packaging, testing, memory application products design, development, compatibility testing, and finally to production. Customers enjoys the only high performance DRAM module provider that emphasizes the overall end-user experience. From developing our award winning memory testing program to innovative fabrication process, each of our final modules offers the same
superior quality output which has made GeIL the fastest-growing DRAM manufacturer in Asia: growing at twice the rate as the average DRAM company in the mist of a stalling economy.

Industry Leader
GeIL is among the drivers in making Double Data Rate (DDR) DRAMs the fastest-growing DRAM architecture on the computing market today. With un-surpassed speed yield of our advanced process technology, GeIL has also been instrumental in establishing new speed categories for DRAMs, e.g. DDR366 and the fastest speed DRAMs on the market today, the 400MHz-clock Enhanced Latency DRAM, staying ahead of standardization committees defining the architectures and performance features for tomorrow's DRAMs - and beyond.

GeIL - Golden Emperor International Ltd GeIL is one of the most professional memory module houses in Taiwan that has been concentrating in memory modules design and manufacturing. Our heritage in memory module design and manufacturing began in 1997 and succeeded creating high-end brand modules of GL2000 and Golden GeIL in 1999 which are now a vogue of the time in Mainland China. Currently, our manufacturing facilities employ over 200 people and produce a wide variety of modules with distribution in over 50 countries. Our diverse product line includes the memory modules of desktop, laptop, server system, and workstation. In order to produce this wide range of performance products, GeIL has implemented a stringent, company-wide, quality control standard of excellence. Only after a module meets or exceeds the company’s rigid requirements for quality and performance, is it then entered into production. At GeIL, our management philosophy is designed to ensure customer satisfaction and to maintain our long-lasting commitment to excellence. We understand the needs of our customers and the importance of delivering high-quality memory modules you can trust. By combining our strict quality standards with the use of state-of-the-art technology, we are able to produce some of the most advanced designs and modules available. This in turn allows us to ensure that every GeIL customer receives all of the quality, performance and dependability they deserve.

:: Technology ::

Functional Description
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. This architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition and command descriptions.

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:

  • VDD and VDDQ are driven from a single power converter output VTT meets the specification
  • A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and VREF tracks VDDQ/2
    - or -The following relationship must be followed:
  • VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V
  • VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V
  • VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any executable command. During the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation.

Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts.